Wireless Transceiver Hits 120 Gbps, Rivaling Fiber Optics


TL;DR

  • Breakthrough Achievement: UC Irvine researchers developed a wireless transceiver operating at 140 GHz that achieves 120 Gbps speeds, matching fiber optic performance.
  • Technical Innovation: The team eliminated the power-hungry DAC bottleneck by constructing signals directly in the radio-frequency domain using only 230 milliwatts.
  • Manufacturing Advantage: The transceiver was fabricated on a standard 22nm node, making it more accessible to manufacture than advanced 2nm or 18A processes.
  • Future Applications: The technology aligns with emerging 6G standards and could enable wireless data center connections and ultra-fast device communication.

UC Irvine engineers announced last Wednesday they developed a wireless transceiver achieving 120 Gbps speeds, matching fiber optic performance for the first time in wireless data transmission. The transceiver operates at 140 GHz and reaches speeds 24 times faster than 5G mmWave.

Payam Heydari, director of UC Irvine Nanoscale Communication Integrated Circuits Labs, explained the technology’s transformative potential for high-speed wireless communication, describing it as a “wireless fiber patch cord.”

“We call this technology a ‘wireless fiber patch cord’ because it offers the blistering speed of fiber optics without the physical cables. By operating in the F-band – a frequency range well above current 5G standards – we can offer massive bandwidths that will transform how machines, robots and data centers communicate.”

Payam Heydari, director, UC Irvine Nanoscale Communication Integrated Circuits Labs (via UC Irvine Samueli School of Engineering)

The F-band operation aligns with emerging 6G development. Reaching the 100-gigabit-per-second milestone required fundamentally rethinking circuit topology to overcome severe power trade-offs plaguing high-speed designs. The team envisioned novel all-analog architectures to prevent the chip from overheating.

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DAC Bottleneck Eliminated

Achieving these speeds required solving a fundamental hardware problem that has long constrained wireless performance. Conventional wireless transmitters face a fundamental limitation when attempting speeds above 100 Gbps. Digital-to-analog converters that create radio signals at these speeds consume several watts of power and generate excessive heat, making them unsuitable for mobile devices.

Zisong Wang, lead author of the UC Irvine wireless transceiver research, explained the DAC bottleneck challenge.

“The Federal Communications Commission and 6G standards bodies are looking at the 100-gigahertz spectrum as the new frontier. But as such speeds, conventional transmitters that create signals using digital-to-analog converters are incredibly complex and power-hungry, and face what we call a DAC bottleneck.”

Zisong Wang, lead author, UC Irvine wireless transceiver research (via Tom’s Hardware)

To bypass this constraint, the team replaced the DAC entirely by constructing signals directly in the radio-frequency domain using three synchronized subtransmitters. The approach, called RF-domain 64QAM, requires only 230 milliwatts to operate. Zisong Wang likened the method to packing a suitcase perfectly before leaving home rather than organizing items while rushing to the airport.

Components of the receiver chip of the wireless transceiver system developed by UC Irvine electrical engineers include the RXFE, receiver front-end; VGA, variable gain amplifier; CTLE, continuous-time linear equalizer; CDR, clock and data recovery; and BB, base band. (Payam Heydari / UC Irvine)

Power-Efficient Receiver Architecture

While the transmitter breakthrough eliminated the digital-to-analog converter (DAC) bottleneck, matching power efficiency on the receiver proved equally challenging. Traditional receivers use analog-to-digital converters that burn watts of power when digitizing 120 Gbps signals.

Youssef Hassan explained that traditional receivers struggle with substantial energy-draining components. These systems hit a physical sampling bottleneck at extreme speeds where digitizing signals requires power far too high for smartphones.

The team developed a power-efficient receiver using hierarchical analog demodulation, breaking signals down hierarchically in the analog domain before digitization. Payam Heydari noted that traditional methods would drain device batteries in minutes, requiring analog-domain processing for mobile applications. The hierarchical analog demodulation technique consumes just 230 milliwatts, efficient enough for portable devices.

Manufacturing Accessibility and Applications

Beyond the technical achievement, the accessibility of this technology sets it apart from other recent developments. The transceiver was fabricated on 22nm node using fully depleted silicon-on-insulator technology. Unlike advanced 2nm and 18A nodes from TSMC and Samsung, this approach uses standard manufacturing processes, making production more accessible.

This manufacturing advantage could accelerate commercialization. Data center operators could use the technology to replace fiber optic cabling between server racks with ultrafast wireless links, reducing hardware, cooling and power costs.

The technology aligns with 6G standards development and could support ultra-fast links between devices, robots, autonomous systems and data centers. High-frequency transceivers are needed for autonomous vehicles and AI edge computing.

Despite these promising applications, practical deployment faces constraints. Current 5G mmWave range limitations of about 300 meters suggest deployment will favor short-range scenarios like data centers over wide-area coverage. The Wi-Fi 7 standard reaches theoretical speeds of 30 Gbps, making UC Irvine’s 120 Gbps achievement four times faster.

Research Team and Publication

Payam Heydari, director of UC Irvine Nanoscale Communication Integrated Circuits Labs and UC Irvine Chancellor’s Professor of electrical engineering and computer science, led the research. Zisong Wang, now at Marvell Technology Inc., served as lead author of the transmitter paper. Youssef Hassan, currently with Qualcomm, led the receiver research. Doctoral student Mohammad Oveisi co-authored the antenna-to-bits paper.

The team published two papers in IEEE Journal of Solid-State Circuits describing the bits-to-antenna transmitter and antenna-to-bits receiver. The team began formulating the concept in 2020 after recognizing traditional mixed-signal chip architectures would hit a performance wall.

The development was funded by the Department of Defense Microelectronics Commons program. FCC and 6G standards bodies are now evaluating F-band spectrum allocations that could enable commercial deployment within the next decade.



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